SD/eMMC - GlobalFoundries 12LP, North/South Poly Orientation
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and…
- GlobalFoundries
- 12nm
- LP
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
SD/eMMC - GlobalFoundries 12LP, North/South Poly Orientation
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and…
GF 22FDX 1.8V/3.3V SD/eMMC PHY AG2 Platform
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
PCIe 5.0 PHY, GF 12LP+ x1, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
25G MR Ethernet PHY, GF 14LPP x4 North/South (vertical) poly orientation
The multi-lane Multi-Protocol 25G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
25G MR Ethernet PHY, GF 14LPP x2 North/South (vertical) poly orientation
The multi-lane Multi-Protocol 25G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
25G MR Ethernet PHY, GF 14LPP x1 North/South (vertical) poly orientation
The multi-lane Multi-Protocol 25G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
28G LR Ethernet PHY, GF 12LP+ x4 North/South (vertical) poly orientation
The multi-lane Multi-Protocol 32G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
28G LR Ethernet PHY, GF 12LP x4 North/South (vertical) poly orientation
The multi-lane Multi-Protocol 32G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…
MP10, USB 3.1/PCIe 3.0 PHY, GF 22FFDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, GF 22FFDSOI X1, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express 3.1 includes the vendor’s high-speed, high-performance transceiver to meet today’s appli…
PCIe 2.0/ CEI 6G, GF 22FDSOI x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 6G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs…
GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V LVDS Transceiver.
To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and…
28G LR Ethernet PHY in GF (12nm)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
The multi-lane Synopsys Multi-Protocol 25G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for hig…
PCIe 4.0 PHY in GF (14nm, 12nm)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’…
The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’…
PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet to…
USB-C 3.1/DP TX PHY in GF (22nm)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB 3.1 PHY (10G/5G) in GF (22nm)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.