MIPI D-PHY Bidirectional 4 Lanes in Fujitsu (40nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
PCIe 2.0 PHY in Fujitsu (40nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet to…
NVM OTP in Fujitsu (90nm, 65nm, 55nm, 40nm)
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in stand…
3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
3.3V to 1.1V / 600mA PWM, Switching Regulator using MIFS C40LP Logic Process
3.3V to 1.1V / 600mA PWM, Switching Regulator using MIFS C40LP Logic Process
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process
MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process