Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track ECO Cell Library.
- UMC
- 28nm
- HLP
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track ECO Cell Library.
Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track ECO Cell Library.
Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track ECO Cell Library.
Standard Cell (ECO) Library IP, RVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic process 9-Track ECO_M1 Core Cell Library (C38).
Standard Cell (ECO) Library IP, RVT, 9 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 9-Track ECO_M1 Cell Library (C35).
Standard Cell (ECO) Library IP, UMC 0.13um eHV process
UMC 0.13um High-Voltage process ECO Cell Library with metal-1 start.
Standard Cell (ECO) Library IP, UMC 0.11um SP/FSG process
UMC 0.11um SP/FSG process mini-lib ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, 6 tracks, UMC 0.11um eFlash process
UMC 0.11um eFlash/EE2PROM AL process ECO_M1 Mini-Library+ (6-Track) Library.
GSMC 0.13um Low Power Process Delay Cells
G13LPV33_DELAYRC_01 is to generate rise/fall delay ranging from 0.15ns to 5ns.
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 65nm LP process
UMC 65nm LP/RVT Low-K Logic process UHS (Ultra high speed) Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 65nm SP process
UMC 65nm SP/HVT Low-K Logic process high speed Cell Library.
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Low-K process high speed Core Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process Mini-Library Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 8 tracks, UMC 65nm LL process
UMC 65nm LL-HVT Low-K process Mini-Library Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 65nm SP process
UMC 65nm SP/RVT process Core Cell Library mini Library.
Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process Mini-Library Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 8 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Low-K process Mini-Library Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um LL/FSG process
UMC 0.13um LL FSG Logic process Enhanced Mini-Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um HS/FSG process
UMC 0.13um HS process Generic Core Cell Library (enhanced Mini-Library).
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG process enhanced Mini-Library.