SMIC 40nm Low Leakage HD, channel length 50nm, HVT Logic Process Standard cell Library
- SMIC
- 40nm
- Silicon Proven
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
SMIC 40nm Low Leakage HD, channel length 50nm, HVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, RVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, PMK,RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, PMK,RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, HVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, ECO,RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, ECO,RVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, ECO,LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, ECO,LVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, ECO,HVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, ECO,HVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, A12T PEK LVT Logic Process Standard Cell Library
SMIC 40nm Low Leakage A12T PEK LVT Logic Process Standard Cell Library
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm SP process
UMC 90nm SP/HVT Low-K process POWERSLASH Core Cell Library libary.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process Low Power standard Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process
UMC 90nm LL/HVT Low-K Logic process Cell Library POWERSLASH Core Cell Library (high density Version).
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm SP process
UMC 65nm SP/HVT process POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process
UMC 65nm SP/RVT Low-K Logic process Powerlash Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm LL process
UMC 65nm LL/HVT Low-K Logic process POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process Mini-Library POWERSLASHKit.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process UHS Library POWERSLASH cells.
Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Logic process 7-Track POWERSLASH Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Logic process 7-Track POWERSLASH Cell Library.