Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL FSG process high density Generic Core Cell Library.
- UMC
- 130nm
- LL
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL FSG process high density Generic Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process metal programmable (M3/M4/M5) cell array standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high performance Core Cell Library.
Standard Cell (Generic) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL Logic Low-K RVT process standard Core Cell Library.
Standard Cell (Generic) Library IP, RVT, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process Standard Cell Library.
Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic process 9-Track Standard Generic Core Cell Library (C30).
Standard Cell (Generic) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C40).
Standard Cell (Generic) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C35).
Standard Cell (Generic) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C30).
Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic process 12-Track Standard Generic Core Cell Library (C30).
Standard Cell (Generic) Library IP, LVT, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process Standard Cell Library.
Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 9-Track Standard Generic Core Cell Library (C38).
Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 9-Track Standard Generic Core Cell Library (C30).
Standard Cell (Generic) Library IP, LVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 9-Track Standard Generic Core Cell Library (C35).
Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C40).
Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C35).
Standard Cell (Generic) Library IP, LVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C30).