Fast Fourier Transform IP Core

The Fast Fourier Transform IP Core implements the Decimation in Frequency - Fast Fourier Transform based on the Cooley-Tukey algorithm. The FFT/IFFT core expects complex samples as input and provides transformed complex samples as output. It performs the transform using log₂ (transform length) stages in pipeline.

• Supports forward and inverse complex FFT
• Supports transform length (N) from 23 to 2¹⁶
• Supports scaled or unscaled IFFT output
• Implemented as pipelined streaming IO architecture

• Run-time configuration of the transform mode (Forward or Inverse FFT) and transform length
• Continuously stream input and output data. The core starts processing immediately after receiving the first sample and does not wait until it receives the entire frame
• Twiddle factors can be stored in ECC ROMs
• Low-power and low-complexity design
• AXI4-Stream handshaking interfaces for seamless integration
• Works with the Creonic DVB-S2X Multi-Carrier Demodulator and Creonic DVB-RCS2 Multi-Carrier Receiver
• Available for ASIC and FPGAs (AMD Xilinx, Intel and Microchip on request)

• Multi-Carrier Transmitter and Receiver Systems
• Spectrum Analysis
• Signal Filtering
• Data Compression

• VHDL source code or synthesized netlist
• HDL simulation models e.g. for Aldec’s Riviera-PRO
• VHDL testbench
• Bit-accurate Matlab, C or C++ simulation model
• Comprehensive documentation