Vendor: SmartDV Category: UART

Ethercat Synthesizable Transactor

The Ethercat Synthesizable Transactor is compliant with V1.0.3 specifications and verifies Ethercat interfaces.

Overview

The Ethercat Synthesizable Transactor is compliant with V1.0.3 specifications and verifies Ethercat interfaces. EtherCAT is build on top of it to make it robust. EtherCAT Synthesizable Transactor provides a smart way to verify the Ethercat component of a SOC or a ASIC in Emulator or FPGA platform. Ethercat Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Key features

  • Supports ETG.1000 S(R) V1.0.3 specification
  • Supports Low Voltage Differential signaling interface
  • Supports MII, MDIO RMII and RGMII Interface as per the ISO/IEC 8802-3 specification
  • Supports RMII and RGMII Interface
  • Supports Manchester Biphase L encoding and decoding
  • Supports EtherCAT frame inside an Ethernet frame
  • Supports EtherCAT frame inside an UDP datagram
  • Supports all types of EtherCAT frames
  • Supports full duplex mode of operation
  • Supports clause22 and clause45
  • Supports all types of TX and RX errors insertion/detection at each layer
  • Supports Under and oversize frame
  • Supports CRC errors
  • Supports Framing errors
  • Supports conformance tests as per ETG.7000.2 V1.0.6 specification
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

Ethercat Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the Ethercat testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
Ethercat Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about UART IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about UART IP cores

What is Ethercat Synthesizable Transactor?

Ethercat Synthesizable Transactor is a UART IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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