Vendor: SmartDV Category: UART

Ethercat Slave IIP

EtherCAT Slave core is compliant with EtherCAT Standard Specification ETG.1000 S(R) V1.0.4.

Overview

EtherCAT Slave core is compliant with EtherCAT Standard Specification ETG.1000 S(R) V1.0.4. Through its EtherCAT compatibility, it provides a simple interface to a wide range of low-cost devices. EtherCAT Slave IIP is proven in FPGA environment. The host interface of the EtherCAT can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

Ethercat Slave IIP is supported natively in Verilog and VHDL

Key features

  • Supports ETG.1000 S(R) V1.0.4 specification.
  • 8 SYNC Manager
  • 8 FMMU's
  • 8kB Process Data RAM
  • 64 Bit Distributed Clocks
  • Can connect with SPI/I2C/UART interfaces based on application
  • MAC is Compliant with IEEE Standard 802.3.2018 specification
  • Supports EtherCAT frame inside an Ethernet frame
  • Supports all types of EtherCAT data frames
  • Supports the standard TCP-IP and UDP-IP protocols
  • Supports Full duplex transmission
  • Supports Sync Manager and Mailbox
  • Supports Field Bus Memory Management Unit
  • Supports Error Detection using Ethernet’s Frame Check Sequence
  • Supports MII and RMII Interfaces for Ethernet PHY
  • Supports conformance tests as per ETG.7000.2 V1.0.6 specification
  • Provides detailed statistics as per the specification
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices

Block Diagram

EtherCat Slave IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The EtherCAT interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
EtherCat Slave IIP
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about UART IP core

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SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about UART IP cores

What is Ethercat Slave IIP?

Ethercat Slave IIP is a UART IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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