Vendor: SmartDV Technologies Category: UART

Ethercat Slave IIP

EtherCAT Slave core is compliant with EtherCAT Standard Specification ETG.1000 S(R) V1.0.4.

Overview

EtherCAT Slave core is compliant with EtherCAT Standard Specification ETG.1000 S(R) V1.0.4. Through its EtherCAT compatibility, it provides a simple interface to a wide range of low-cost devices. EtherCAT Slave IIP is proven in FPGA environment. The host interface of the EtherCAT can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

Ethercat Slave IIP is supported natively in Verilog and VHDL

Key features

  • Supports ETG.1000 S(R) V1.0.4 specification.
  • 8 SYNC Manager
  • 8 FMMU's
  • 8kB Process Data RAM
  • 64 Bit Distributed Clocks
  • Can connect with SPI/I2C/UART interfaces based on application
  • MAC is Compliant with IEEE Standard 802.3.2018 specification
  • Supports EtherCAT frame inside an Ethernet frame
  • Supports all types of EtherCAT data frames
  • Supports the standard TCP-IP and UDP-IP protocols
  • Supports Full duplex transmission
  • Supports Sync Manager and Mailbox
  • Supports Field Bus Memory Management Unit
  • Supports Error Detection using Ethernet’s Frame Check Sequence
  • Supports MII and RMII Interfaces for Ethernet PHY
  • Supports conformance tests as per ETG.7000.2 V1.0.6 specification
  • Provides detailed statistics as per the specification
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices

Block Diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The EtherCAT interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
EtherCat Slave IIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force one-size-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

Learn more about UART IP core

Capturing a UART Design in MyHDL & Testing It in an FPGA

The universal asynchronous receiver/transmitter (UART) is an old friend to embedded systems engineers. It's probably the first communications protocol that we learn in college. In this article, we will design our very own UART using MyHDL.

Integrating Post-Quantum Cryptography (PQC) on Arty-Z7

Post-quantum cryptography (PQC) is moving from theory to engineering reality. With NIST-standardized algorithms ML-KEM (FIPS 203) and ML-DSA (FIPS 204) now finalized, FPGA developers face a practical challenge: How to integrate these algorithms efficiently on resource-constrained hardware?

How to design secure SoCs, Part V: Data Protection and Encryption

In today’s connected world, where data is a crucial asset in SoCs, Part V of our series explores how to protect and encrypt data, whether at rest, in transit, or in use building on our earlier blog posts of the series: Essential security features for digital designers, key management, secure boot, and runtime integrity.

Not all overvoltage tolerant GPIOs are the same

Most foundries provide GPIO libraries to their fabless customers. These libraries contain different elements like supply/ground pads, analog I/Os, digital I/Os, corner cells, filler cells, power-on-reset circuits. Frequently the foundry includes cells for different voltage domains. In 40nm CMOS the IC designer can use cells for 1.8V, 2.5V and 3.3V for instance.

Frequently asked questions about UART IP cores

What is Ethercat Slave IIP?

Ethercat Slave IIP is a UART IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP