Overview
The MW_DVBS2 modulator core performs the digital baseband functionality for the transmission side of Digital Video Broadcasting Satellite link. The modulator core implements the framing functions as defined by ETSI EN 302 307 V1.1.1 (2009-08). It is configurable to supports all several configurations regard to constellation, 4QAM, 8PSK, 16 APSK and 32APSK, code rate, 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 5/6, 8/9 and 9/10. The error protection used is completely new, based on LDPC algorithm followed by the bit interleaver. Squared-root raised cosine filter, with roll-off factors 0,35 or 0,25 or 0,20 is used. Microblaze or external processor interface, with status and control registers, is available for controlling and managing the core. TS over IP is available, for IP based contribution. ASI interface is available also. Internal 20-bit architecture for high level MER and BER performances. FPGA netlist only or complete design environment package are deliverable.
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An efficient IP reuse strategy relies on IP blocks with wide applicability. That makes generic blocks, such as programmable processors preferable. However, in many applications such as handheld wireless terminals, additional silicon area and power consumption compared to fixed function solutions can not be accepted.
