Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
Logicircuit, Inc.
Category:
SRAM
DO-254 Distributed Memory Generator 1.00a
Creates a variety of memory structures using Select RAM.
Overview
Creates a variety of memory structures using Select RAM. Basically if you need a small memory, LUTs can be turned into 32 bit memory blocks. This IP generates those.
Key features
- Generates Read Only Memories (ROMs), Single, Simple Dual and Dual-port Random Access Memories (RAMs), and SRL16-based RAMs
- Supports data depths ranging from 16 to 65,536 words
- Supports data widths ranging from 1 to 1024 bits
- Optional registered inputs and outputs
- Example Design helps you get up and running quickly
Benefits
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
What’s Included?
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.
Specifications
Identity
Part Number
10125
Vendor
Logicircuit, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about SRAM IP core
Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
Why SRAM PUF Technology Is the Bedrock of Dependable Security in Any Chip
Vincent van der Leest, Synopsys
AI-driven SRAM demand needs integrated repair and security
Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.
A comparison of SRAM vs quantum-derived semiconductor PUFs
This article explores the relative performance of SRAM PUF and quantum-derived semiconductor PUF technologies for IoT security.
Basics of SRAM PUF and how to deploy it for IoT security
This article covers the basics of what an SRAM PUF (physical unclonable function) is and how it works, as well as the functionality it offers in internet of things (IoT) security as the trust anchor for any device.
Frequently asked questions about SRAM IP cores
What is DO-254 Distributed Memory Generator 1.00a?
DO-254 Distributed Memory Generator 1.00a is a SRAM IP core from Logicircuit, Inc. listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.