Vendor: SmartDV Category: UART

DMX Synthesizable Transactor

DMX Synthesizable Transactor provides a smart way to verify the DMX component of a SOC or a ASIC in Emulator or FPGA platform.

Overview

DMX Synthesizable Transactor provides a smart way to verify the DMX component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DMX Synthesizable Verification IP is fully compliant with standard DMX Specification and provides the following features.

Key features

  • Fully compatible with American National Standard E1.11 - 2008 (R2013) Specification
  • Supports transmit and receive commands that allow the user to transmit and receive DMX512 packets
  • Supports fully configurable serial interface
  • Supports programmable clock frequency of operation
  • Supports configurable baud rate
  • Supports the reset sequence
  • Supports all reserved alternative start codes
  • Supports up to maximum of 513 slots
  • Supports ASCII Text character set encoding technique
  • Supports UTF-8 Text character set encoding technique
  • Supports all types of error insertion and detection
    • Minimum break length error
    • Maximum break length error
    • Invalid start code error
    • Maximum mark before break error
    • Minimum mark after break error
    • Maximum mark after break error
    • Break to break timeout errors
    • DMX512 packet timeout errors
    • Start bit error
    • Stop bit error
    • 16-Bits checksum error
    • 8-Bits checksum error
    • Wrong SIP sequence number error
    • Timeout errors
  • Supports glitch insertion and detection

Block Diagram

DMX Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the DMX testcases
  • Examples showing how to connect and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Specifications

Identity

Part Number
DMX Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about UART IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about UART IP cores

What is DMX Synthesizable Transactor?

DMX Synthesizable Transactor is a UART IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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