Overview
The Distributed Memory Generator is provided under the terms of the Xilinx End User License and is included with ISE® and Vivado™ design tools at no additional charge.
The Distributed Memory Generator IP core creates a variety of memory structures using Select RAM. It can be used to create Read Only Memory (ROM), single-port Random Access Memory (RAM), and simple dual/Dual port RAM as well as SRL16-based RAM. Flexible feature set allows users to customize for Memory type, Data width, Memory size, Input/Output options and reset options.
Learn more about SRAM IP core
Single-event effects (SEEs) are of a growing concern in high-reliability system development, yet there is much disparity among users of application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) with regard to understanding how susceptible their designs might be.
Design-level security features in 90nm non-volatile Spartan-3AN FPGAs from Xilinx address the issues of overbuilding, cloning, and reverse engineering.
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vincent van der Leest, Synopsys
Increasing popularity of AI applications and DPU architecture has led to growing demand for higher SRAM densities, in turn placing challenges on SRAM yield and reliability.
