DisplayPort Receiver IP

Our 6th generation DisplayPort Receiver Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPort 1.5.

Features include link rates up to 20Gbps for DisplayPort 2.0, 8.1Gbps for DisplayPort 1.4a. Display Steam Compression (DSC), multi-stream transport (MST) and more. The base core includes all required link functionality— Main Link, Secondary Channel, and AUX Channel protocols—and supports the HDCP 2.3 standards for data encryption.

The DisplayPort Receiver core interfaces use common industry standards for low-complexity integration.

Video In

Streaming interface with industry-standard flow control, including separate syncs and data enable. Frame and line delimiter signals are supported with either 1, 2 or 4 pixels per input clock cycle.

42-bit pixel inputs provide deep color support. Other color depths are chosen through selective use of these input ports.

Audio

Multi-port I2S interface with up to 32 audio channels for digital audio transport.

Host

32-bit AMBA Peripheral Bus (APB), 4 slave port for low-complexity transfers of configuration information to the core.

• Silicon proven on multiple ASIC and FPGA processes
• Capable of operating without a host CPU in low complexity applications
• Horizontal and vertical video delimiter signals with 1, 2 or 4 pixels per output cycle, supporting up to 16K resolution output; deep color and HDR support
• 1.62 to 8.1 Gbps link rate across 1, 2, or 4 lanes
• Secondary channel support, including audio and camera/video information packets
• MST support for 1 to 4 streams
• HDCP 1.3/2.2/2.3 support in SST and MST modes
• Optional eDP 1.4b supports PSR and PSR2
• DSC transport with Forward Error Correction support
• Interfaces to external PHY implementations in both FPGA and ASIC platforms
• Compatible with 3rd party PHYs

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• HDL source files for the function design
• Fully functional models for block-level and top-level testing, including over 120+ tests in the user level environment
• Functional specification
• Timing constraints summary document
• IP-XACT register descriptions
• Generic SRAM simulation models
• C Reference Driver