DisplayPort 2.1b IP Core

Direct connection to DisplayPort devices using the Bitec DisplayPort core.

DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, DELL, Apple etc) DisplayPort is not hindered by license and royalty fees.

The Bitec DisplayPort IP core enables DTV manufacturers to rapidly develop and deliver displays offering a superior viewing experience within ever-shrinking product lifecycles.

The Bitec DisplayPort IP core accepts 1,2 or 4 lanes at either 1.62, 2.7, 5.4 or 8.1 Gbps or 10, 13.5 and 20Gbps in 128b/132b mode (includes eDP additional rates), in compliance with the DisplayPort 2.1 specification.

Video data is input to the core Transmitter as parallel data with H-sync, V-sync and Data Enable signals. Audio and secondary data streams are also supported and available for transport.

The core Receiver can output received video data on a stream interface for convenient interfacing to downstream logic. Audio and all Secondary Data are available in parallel format on their respective outputs. Both Receiver and Transmitter can use optional AUX debug ports for run-time AUX message log and monitoring.

Multi-Stream (MST) applications

The Bitec DisplayPort IP Core Receiver supports Multi-Stream, a powerful DisplayPort v.2.1b feature allowing to transfer video and audio content for more than one display using only a single cable. For instance, four Full-HD streams (1920 x 1080p @ 60 Hz) can be delivered to the Receiver using Multi-Stream or a single 4K@60 stream (3840 x 2160 @ 60 Hz) using either Multi- or Single-Stream mode.

Clock Recovery support

A Clock Recovery block is available for the Bitec DisplayPort IP Core Receiver when the application requires DisplayPort received video data to be output together with the synthesized original pixel clock. This feature is useful, for instance, for outputting HDMI and analog video without using a frame buffer. The clock recovery feature is licensed separately.

Altera Arria 10 GX DisplayPort Evaluation kit

An evaluation kit is available to allow application development using the Bitec DisplayPort IP Core. The kit includes an Arria 10 GX development kit (Stratix V available on request), a Bitec DisplayPort FMC daughtercard and a DisplayPort cable. An Opencore evaluation Bitec DisplayPort IP Core is requried. The Opencore evaluation gives full functionality of the core under the standard Opencore terms. The Bitec DisplayPort Daughter Card allows easy interfacing to standard source and sink devices . Bitec also offer a tailoring service for bespoke designs. Contact Bitec for more details.

Various reference designs are available which demonstrate

• Full DP 2.1b functionality
• Link rates to 10Gbps
• Multistream Video Receiver and Transmitter
• 8K@30 loopthrough
• Pixel Clock recovery
• DP++ using the Bitec HDMI IP Core
• Display Stream Compression (Upon request)

AMD ZCU102 DisplayPort Evaluation kit

• Full DP 2.1b functionality
• Link rates to 13.5Gbps
• Multistream Video Receiver and Transmitter
• 8K@30 loopthrough
• Pixel Clock recovery
• DP++ using the Bitec HDMI IP Core
• Display Stream Compression (Upon request)

Receiver Features

• Support for 1, 2, and 4 lanes operation
• Support for 8b10b: 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, 6.75 Gbps and 8.1 Gbps
• Support for 128b/132b : 10Gbps, 13.5Gbps and 20G
• Support for 6, 8, 10, 12 and 16 bits-per-colour
• Support for RGB and YCbCr colour encoding, 4:4:4, 4:2:2 and 4:2:0
• Support for RAW and Y-only colour encoding with 6, 8, 10, 12 and 16 bits-per-pixel
• Support for RAW with 32 bits-per-pixel
• Support for YCbCr 4:2:2 and RGB with 9 bits-per-colour
• Support for 1, 2 or 4 pixels parallel output
• Support for 3D Stereo Video
• Support for LPCM, HBR, LPCM 3D, One Bit and DST Audio
• Support for SDP splitting
• Support for Adaptive-Sync
• Support for Forward Error Correction (FEC)
• Support for Display Stream Compression (DSC)
• Support for DSC pass-through
• Support for VESA Display Compression-M (VDC-M)
• RTL or MCU-based Link Layer management
• 20-bit, 40-bit 8b10b pcs parallel data interface
• 32-bit, 64-bit 128b132b pcs parallel data interface
• Multi-Stream support (MST, 1 to 4 Sink Streams)
• MSO Support (eDP)
• Power management
• Extensions requiring an additional license:
  • Support for 3 lanes operation
  • Support for max 256-byte long payload for AUX transactions
  • Advanced Link Power Management (ALPM) support (AUX-wake and AUX-less)

Transmitter Features

• Support for 1, 2 and 4 lanes operation
• Support for 8b10b : 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, 6.75 Gbps and 8.1 Gbps
• Support for 128b/132b : 10Gbps, 13.5Gbps and 20Gbps
• Support for 6, 8, 10, 12 and 16 bits-per-colour
• Support for RGB and YCbCr colour encoding, 4:4:4, 4:2:2 and 4:2:0
• Support for RAW and Y-only colour encoding with 6, 8, 10, 12 and 16 bits-per-pixel
• Support for RAW 32 with bits-per-pixel
• Support for YCbCr 4:2:2 and RGB with 9 bits-per-colour
• Support for 1, 2 or 4 pixels parallel input
• Support for 3D Stereo Video
• Support for LPCM, HBR, LPCM 3D, One Bit and DST Audio
• Support for SDP splitting
• MCU-based Link Layer management
• Accepts traditional hsync/vsync/de video and proprietary Video Image formats
• Support for Adaptive-Sync
• Support for Forward Error Correction (FEC)
• Support for Display Stream Compression (DSC)
• Support for DSC Playback and DSC pass-through
• Support for VESA Display Compression-M (VDC-M)
• 20-bit, 40-bit 8b10b pcs parallel data interface
• 32-bit, 64-bit 128b132b pcs parallel data interface
• Multi-Stream support (MST, 1 to 4 Source Streams)
• MSO Support (eDP)
• LTTPR support
• Power management
• Extensions requiring an additional license:
  • Support for 3 lanes operation
  • Support for max 256-byte long payload for AUX transactions
  • Advanced Link Power Management (ALPM) support (AUX-wake and AUX-less)

• 1,2,3 & 4 lanes
• 1.62, 2.7, 5.4 and 8.1 Gbps link rate (includes eDP rates)
• 10,13.5 and 20Gbps in 128b/132b mode
• HDCP 1.3 / 2.3
• MST support, up to 4 streams
• 6, 8, 10, 12 & 16 bit color depths
• Forward Error Correction (FEC)
• Display Stream Compression (DSC)
• ASIC Version available
• ALPM Support
• Fully VESA Certified
• Technology Support: Altera/Intel GX devices, AMD/Xilinx FPGA, Microchip PolarFire, Lattice ECP5, ASIC