Overview
MW_ASI/SMPTE_SERDES cores implements related standards, by means of a precise and robust design, to inexpensive devices, (from Spartan3 up to 7Series families) using reduced FPGA resources.
This implies, at system level, two major benefits:
– No external deserializer devices are required
– Several instances of the core can be mapped in the same low-cost FPGA
MW_ASI/SMPTE_SERDES_RX performs three major tasks:
– Recovery and resampling serial data
– Framing data in the correct word boundary
– Decoding the 8B/10B encoded word
– TS flow delineation and synchronization
– TS flow adapting to user clock
MW_ASI/SMPTE_SERDES_TX adapts TS flow from yser clock to transmission clock, encodes words in 8B/10B format and serializes the data for transmission.
Clock infrastructures (PLLs, DCMs, BUFGs) are common to all core instances.
Provider
Mindway is a fast growing company focused on FPGA based IP core design, verification and integration services.
Mindway’s mission is to supply state-of-art, cost-effective silicon solutions, allowing customers to build complex, innovative and high-margin products, and improve technology contents of designs.
Mindway offers a large IP core portfolio for Audio, Video, Broadcast, Internet Protocol and Telecom application. Mindway’s main goal is to design IP with size and frequency optimization, in order to map them on mainstream Xilinx Spartan devices or to save resources on high level Xilinx Virtex family.
Founded in 2005, Mindway, took over the design and consulting activity of Siscad (started in 1984), leveraging a strong background of more than 20 years of design skills in several different fields like Telecom, Broadcast, Aerospace, Home Automation, Industrial and Transportation.
Mindway has joined the Xilinx Alliance Program and recently the SignOnce Professional Services Agreement (PSA); moreover, as Xilinx authorized training provider, offers specialized educational trainings.
Mindway is headquartered in Agrate Brianza (Milan, Italy) at “Centro Direzionale Colleoni” business centre.
Learn more about Broadcast IP core
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In this paper, we developed low power transport demultiplexer to support MPEG-2 transport streams for ATSC and DVB digital broadcast standards. Novel window based packet identification (PID) and section filtering is presented to provide a cost effective and flexible solution.
In this paper, we developed low power transport demultiplexer to support MPEG-2 transport streams for ATSC and DVB digital broadcast standards. Novel window based packet identification (PID) and section filtering is presented to provide a cost effective and flexible solution.
The proliferation of high-definition television (HDTV) video content creation and the method of delivering these contents in a bandwidth-limited broadcast channel environment have driven new video compression standards and associated video image processin
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