Processor Architecture for High Performance Video Decode
Processor Architecture for High Performance Video Decode
Vendor:
Zipcores Electronic Systems Engineering S.L.
Category:
Filters Transforms
Digital Down Converter with configurable Decimation Filter
The DDC_DEC IP Core is a complex-valued digital down converter with a configurable number of decimation stages.
Overview
The DDC_DEC IP Core is a complex-valued digital down converter with a configurable number of decimation stages. The design is ideal for high sample-rate applications and permits a digital input signal to be mixed-down and re-sampled at a lower data rate. The DDC_DEC is suitable for the down-conversion of any digitally modulated signal to baseband or other intermediate frequencies.
The IP Core features a high-precision 16-bit DDS oscillator for the digital mixing stage. This oscillator is fully programmable and offers excellent phase and frequency resolution. The digital mixing stage is a complex multiplier that allows the mixing of both real and imaginary (I/Q) inputs. If only real inputs are required, then the imaginary input (q_in) should be tied low.
The output decimation stage features a configurable decimate-by-2N poly phase filter for both I and Q channels. Each filter stage is highly optimized to use only 12 multipliers while still achieving 80 dB of stop band attenuation.
The design features two clock-enable signals. The signal en is the global clock-enable and may be used to enable/disable sampling for the whole circuit. The output clock-enable signal en_out is only asserted when the decimated output samples are active. For instance, when decimating by a factor of 2, then this signal will have a 50% duty cycle. When decimating by a factor of 4 it will have a 25% duty cycle and so on.
Key features
- Synthesizable, technology independent IP Core for FPGA, SoC and ASIC
- 16-bit signed input/output data samples
- Digital oscillator with > 100 dB SFDR
- Digital oscillator phase resolution of 2π/216
- Digital oscillator frequency resolution of Fs/232
- Integrated FIR decimation filter with configurable decimation factors from 0 to 2N
- Highly optimized design requiring only 12 multipliers per decimate-by-2 stage
- Each decimate-by-2 filter stage has 80 dB of stop-band attenuation
- Typical sample rates of 300 MHz+ on low-cost FPGAs and SoCs
Block Diagram
DDC_DEC block diagram
Applications
- Digital I/Q Demodulators
- Compatible with any digital modulation scheme e.g: FSK, PSK, QAM, WiMAX, WCDMA, COFDM etc.
- Conversion of IF signals to baseband frequencies for subsequent processing
Specifications
Identity
Part Number
DDC_DEC
Vendor
Zipcores Electronic Systems Engineering S.L.
Type
Silicon IP
Files
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Provider
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Frequently asked questions about Filters and Transforms IP cores
What is Digital Down Converter with configurable Decimation Filter?
Digital Down Converter with configurable Decimation Filter is a Filters Transforms IP core from Zipcores Electronic Systems Engineering S.L. listed on Semi IP Hub.
How should engineers evaluate this Filters Transforms?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Filters Transforms IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.