UFS 3.1 Silicon Proven 2.1 Device, Host
Key Features
- Compliant with UFS Specification v2.x, 3.x
- Supports up to 2-lanes (restricted by Standard) running at HS-G3 (5.8Gbps)
- AXI Support
- All UPIU Processing
- Datain, Dataout, Command, Response, RTT, Query, Task Management and Reject
- Complete control of UIC Layer by UFS Host
- Error Reporting and Handling Supported
- Priority arbitration between command, query and task management UPIUs and Indexed based processing within Command and Query UPIUs.
- Supports 32 UTP Transfer request descriptors and 8 UTP Task Management Descriptors for UFS host
- Supports Boot LUN, RPMB Well-known LUNs.
- Device: Up to 8 LUNs configurable. Up to 8 command queue in each LUN. Up to 8 tasks handling for task management.
- Priority LUN handling.
- Security Features
Block Diagram
Technical Specifications
Maturity
Silicon Proven, FPGA validated, Interop tested, Design verified
Availability
Immediately
Related IPs
- UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
- UFS 2.1 Device Controller compatible with MIPI M-PHY 3.1 and UniPro 1.6
- UFS 3.1 Silicon Proven 2.1 HOST
- UFS Host 2.1 Prototyping Kit (HDK )Total IP in a Box
- USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 14SF+
- USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 12SF++