IP Catalog > Interface IP Cores > UALink IP Cores > UALink PCS IP Core

UALink PCS IP Core

Overview

Silicon agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification

The UA Link PCS IP Core is a high-performance, silicon-agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification. Designed for seamless integration into accelerator, switch, and SoC designs, it delivers deterministic low-latency, robust error correction, and compatibility with multiple high-speed Ethernet-derived link rates.

This IP core bridges the UALink Data Link Layer (DL) to the Physical Medium Attachment (PMA), ensuring optimized flit-to-codeword mapping, forward error correction (FEC), and alignment marker handling as defined in UALink_200 Standard. It is ideal for systems requiring 200–800 Gbps per Link/Station with industry-leading signal integrity and interoperability.

Key Features

  • UALink_200 Specification Compliant: Implements PCS functions per Rev 1.0
  • Multi-Rate Support :
    • 100 GBASE-KR1/CR1, 200 GBASE-KR2/CR2, 400 GBASE-KR4/CR4,
    • 200 GBASE-KR1/CR1, 400 GBASE-KR2/CR2, 800 GBASE-KR4/CR4
  • Low-Latency FEC 1-way & 2-way interleave options for reduced latency
  • Deterministic Flit Alignment: 640B DL Flit to 680B codeword mapping
  • Standards-Compatible: IEEE 802.3dj PCS & FEC compliant with UALink extensions
  • Integrated Lane Alignment: Lane marker insertion/removal per UALink-defined rules
  • Targeting both ASICs and FPGAs

Benefits

  • Test Environment: UA Link PCS IP is Tested against a VIP model in UVM regression for full functional coverage
  • Silicon Agnostic: Designed in Verilog and targeting both ASICs and FPGAs
  • PHY Integration: PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient  deployment
  • Active Support: All support is actively provided by engineers directly

Block Diagram

UALink PCS IP Core Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format.

The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Chip Interfaces Engineers.
  • Test Report , Synopsys SGDC Files and Synopsys Lint, CDC and Waivers available on request

Technical Specifications

Short description
UALink PCS IP Core
Vendor
Vendor Name
Request Info

Related IPs

×
Semiconductor IP