NIST FIPS-197 Compliant Ultra-Low Power AES IP Core

Overview

ntAES8 core implements NIST FIPS-197 Advanced Encryption Standard. ntAES8 core can be programmed to encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. The ntAES8 has been carefully designed to require minimum logic resources rendering it an ideal solution for ultra-low power applications. This has been achieved by using an 8-bit data path size which means that 16 clock cycles are required to load/unload the 128-bit plaintext/ciphertext block. Noesis is proud to offer an optimum AES IP core solution exhibiting the best performance-silicon area ratio available in the industry due to our unique architectural implementation of the Galois Field Multiplier (the structural datapath element of all AES cryptographic engines) as well as our efficient algorithm mapping techniques.

Key Features

Compliant to Advanced Encryption Standard (AES) (FIPS PUB 197).
Supports both encryption and decryption functions.
Supports 128/192/256-bit Cipher keys.
Processes an 128-bit block in 480/582/684 clock cycles for 128/192/256-bits cipher keys respectively.
Supports ECB, CBC, CFB, OFB and CTR modes.
Optional Key Expansion module.
Supports I/O data flow control capability.
Exhibits highly optimized performance-silicon area ratio.
Ideal for ultra-low power applications.
Fully synchronous design.
Silicon proven in ASIC and FPGA technologies for a variety of applications.

Benefits

ntAES8 IP core exhibits the best performance-silicon area ratio available in the industry.
It is an ideal solution for ultra-low power applications.

Block Diagram

Deliverables

RMM compliant synthesizable VHDL or Verilog source code or FPGA netlist.
VHDL or Verilog test benches and example configuration files.
C++ model.
Comprehensive technical documentation.
Technical support.

Technical Specifications

Foundry, Node

TSMC

Maturity

Silicon proven

Availability

Now