MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
Overview
The MIPI D-PHY Analog TX IP Core adheres fully to version 1.2 of the D-PHY specification. It supports both the MIPI Camera Serial Interface (CSI-2) and the Display Serial Interface (DSI) protocols. This TX PHY comprises one clock lane and four data lanes. The D-PHY integrates an analog front end responsible for generating and receiving electrical level signals, along with a digital back end controlling the I/O functions. Additionally, it features an internal termination resistor with auto-calibration. This MIPI DSI PHY (MIPI TX DPHY) includes a PLL, a Clock Lane, and four Data Lanes for MIPI DSI data transmission. Moreover, the D-PHY can function as a 5V tolerance GPIO bank.
Key Features
- DSI PCS :
- The Register Bank is accessible through a standard AMBA-APB slave interface, providing access to the DSI PHY registers for configuration and control.
- Host_adapter: remapping PPI Signal with lane control and phy_adapter block;
- Lane_ctrl block (clklane_ctrl/datalane0_ctrl/datalane1_ctrl/datalane2_ctrl/datalane3_ctrl)
- acknowledges the operation on PPI interface. It enables a high-speed transmission or low-power transmission/reception and schedules the activities inside the link.
- PHY_adapter: remappig lane_ctrl Signal with phy interface;
- DSI PMA:
- A PLL for high speed clock and MIPI data clock generation
- Data MUX and Reference resistor calibration
- MIPI PHY IO with GPIO compatible
- Silicon Proven in TSMC 22ULP
Benefits
- DSI PCS :
- The Register Bank is accessible through a standard AMBA-APB slave interface, providing access to the DSI PHY registers for configuration and control.
- Host_adapter: remappig PPI Signal with lane control and phy_adapter block;
- Lane_ctrl block (clklane_ctrl/datalane0_ctrl/datalane1_ctrl/datalane2_ctrl/datalane3_ctrl)
- acknowledges the operation on PPI interface. It enables a high-speed transmission or low-power transmission/reception and schedules the activities inside the link.
- PHY_adapter: remappig lane_ctrl Signal with phy interface;
- DSI PMA:
- A PLL for high speed clock and MIPI data clock generation
- Data MUX and Reference resistor calibration
- MIPI PHY IO with GPIO compatible
Block Diagram
Applications
- Automotive
- Mobile
- IoT
- Consumer Electronics
- VR
- AR
Deliverables
- GDSII & layer map
- Place-Route views (.LEF)
- Liberty library (.lib)
- Verilog behaviour model
- Netlist & SDF timing
- Layout guidelines, application notes
- LVS/DRC verification reports
Technical Specifications
Foundry, Node
TSMC 22ULP
Maturity
In Production
Availability
Immediate
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