LTE Turbo Decoder
Overview
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder. The sliding window algorithm is used to reduce the internal memory sizes. Turbo decoder accepts input LLR's with 8-bit precision and outputs the hard decision bits after six full iterations.
Key Features
- 8-bit precision for input LLR
- 13-bit precision for internal calculations
- Provides automatic normalization for internal calculations to avoid hardware overhead
- Supports full 3GPP-LTE and UMTS block size range is supported
- Supports rate 1/3 coded input
- Supports MAX-log-MAP with scaling factor
- 8 parallel-decoding units (with options of 4/2/1 parallel decoding units for smaller block length codes)
- Sliding window algorithm for internal memory reduction
- Uses parallel internal interleaved/de-interleaver
- Payload throughput of up to 43.2 Mbit/s at 6 iterations (111 MHz on Xilinx-XC6VLX760-1FF1760)
- Supports a configurable maximum number of iterations and controllable termination for achieving greater throughput
Deliverables
- Synthesizable Verilog
- System Model (Matlab) and documentation
- Verilog Test Benches
- Documentation
Technical Specifications
Maturity
In Production
Availability
Immediate