This macro-cell is a low noise, high PSRR voltage reference core designed for TSMC 0.18um (CLM18) CMOS technology. The core is ideal for applications where noise performance is critical.
The circuit generates a buffered 1.185V, temperature-compensated bandgap voltage reference (40ppm/°C). A 5-bit trimming is available and guarantees ±1.5% output voltage accuracy. A 25uA reference current source (PTAT) for external use is also included.
The core is easily re-targeted to any other CMOS technology.
