GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF

Overview

The GPHY is a highly integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption. It is capable of operating in 10BASE-T, 100BASE-TX, and 1000BASE-T. This GPHY links the GMII-based Media Access Control Layer (MAC) (Giga Media Independent Interface). This GPHY uses either RGMII or GMII to connect to the Media Access Control Layer (MAC). For 100BASE-TX Fast Ethernet and 1000BASE-T Giga Ethernet, it may support Unshielded Twisted Pair Category 5 Cable (UTP5), or UTP5/UTP3 cable for 10BASE-T Ethernet. It includes the Physical Coding Sub-layer (PCS), Physical Medium Attachment Layer (PMA), Twisted Pair Physical Medium Dependent Sub-layer, and the whole physical layer function of 100BASE-TX described by IEEE802.3u and 1000BASE-T specified by IEEE802.3ab (TP-PMD, 100BASE-TX only).

Key Features

  • IEEE 802.3-2008, IEEE 802.3az fully standards compliant
  • IEEE 1588-2008 support
  • BroadR-Reach™ support
  • Dual port MAC interface: GMII (10/100/1000BASE-T), MII (10/100BASE-T).
  • Auto-negotiation support
  • Automatic detection and correction of pair swaps (Auto-MDIX), pair skew and pair polarity
  • 6 different operating modes: 1000BASE-T Full Duplex and Half Duplex, 100BASE-TX Full Duplex and Half Duplex, 10BASE-T Full Duplex and Half Duplex
  • Management interface
  • Baseline wander compensation
  • On-chip transmit wave-shaping
  • On-chip hybrid circuit
  • 10KB jumbo frames
  • Internal, external and remote loop back
  • Hardware configuration for default operation
  • Power down mode, interrupt support
  • IEEE 1500 support for SoC testing integration
  • LED indication: link mode, status, speed, activity, and collision
  • Silicon Proven in SMIC 28nm SF

Block Diagram

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF Block Diagram

Deliverables

  • Detailed Datasheet
  • Verilog behaviour model (A) for simulation
  • Liberty (db./.lib) for synthesis, STA, and equivalence checking
  • CTL / CTLDB for DFT
  • SPF (Standard Test Interface Language (STIL) Procedure File) for ATPG
  • LEF for APR
  • CDL for LVS connection

Technical Specifications

Maturity
In Production
Availability
Immediate
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Semiconductor IP