CPRI 7.0

Overview

Highly mature, silicon proven and silicon agnostic IP core conforming to CPRI 7.0 specifications

The Common Public Radio Interface (CPRI) 7.0 core is a silicon agnostic implementation of the CPRI 7.0 specification, which is targeting both ASIC and FPGAs CPRI. CPRI is a high-speed serial interface designed to meet or exceed the requirements of base band systems, C-RAN switches, Digital Front-End (DFE) processors or advanced test systems. With its extreme flexibility and reduced logic consumption, the CPRI 7.0 IP core is the perfect match whether the application is REC (Radio Equipment Controller) or RE (Radio Equipment).

The core can be dynamically configured to handle wireless multi-mode radio systems implementing deterministic latency features and high-performance throughputs required by LTE-A and 5G radio base stations.

The CPRI cores come in several versions to suit any implementation scenario whether speed, a compact size or a wide feature set is required.

Key Features

Delivering Performance
- CPRI Specification V7.0 full feature set implemented
- Modular design with full feature set available
- Up to 64 antenna carriers per core
- Supports line-rates 1-10 (up to 24.33024 Gbps)
- Dynamic mapping configuration
Richly Featured
- All mapping methods available (1, 2 and 3)
- Size optimized Ethernet GMII interface
- Accurate delay measurements and calibration
- Daisy Chaining Interface
- Rate Auto-Negotiation
- RS-FEC
- Scrambling
- PCS with Delay Measurement 64B 66B
- Sample Widths 8-16 bits
Easy to use
- Testbench with typical system configuration and examples
- Easy integration
Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs

Benefits

Test Environment: CPRI 7.0 IP is tested against a VIP model in UVM regression for full functional coverage
Silicon Agnostic: Optimized for ASIC but can be synthesized for most FPGAs
Interoperability Tested: Multiple field deployments and tested against CPRI references
Radio Expertise: IP with rich feature set designed by pioneers in radio solutions
Active Support: All support is actively provided by engineers directly

Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format.
The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Synopsys Lint and CDC (optional)

Technical Specifications

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