3.3V->1.5V Cap-less LDO IP Core
Overview
A 3.3V->1.5V Cap-less LDO LDO (Low Drop-Out) is a type of voltage regulator designed to provide a stable output voltage of 1.5 volts from a 3.3-volt input voltage source. It is typically used in low-power applications where a low output voltage is required for digital circuits or other components.
Key Features
- Low Dropout Voltage
- Low Output Voltage
- Low Quiescent Current
- Low Noise
- Thermal Shutdown Protection
- Reverse Current Protection
- Short-Circuit Protection
- Overload Protection
- Wide Operating Temperature Range
- Low Power Consumption
Deliverables
- GDS
- LVS Spice netlist
- Verilog mo
- User Guidelines including: integration guidelines, layout guidelines, testability guidelines, packaging guidelines, board-level guidelines
Technical Specifications
Maturity
In Production
Availability
Immediate
Related IPs
- 3.3V->1.5V Low Power LDO IP Core
- 3.3V - >1.2V/1.1V/0.9V Low Power Cap-less LDO IP Core
- 3.3V ->1.1V/0.9V Cap-less LDO IP Core
- 5V->1.5V Cap-less Ultra-low Power LDO IP Core
- Low Power 5V->3.0V Cap-less LDO IP Core
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core