Vendor: Anchor Hill Communications Category: DAC

DAC Correction Filter

The AH1002-DCF DAC Correction Filter (DCF) FPGA core family provides correction in the discrete-time digital domain for the sin(x…

Overview

The AH1002-DCF DAC Correction Filter (DCF) FPGA core family provides correction in the discrete-time digital domain for the sin(x)/x frequency response of a typical Digital to Analog Converter (DAC). Anchor Hill's DCF cores are implemented as multiplierless Finite Impulse Response (FIR) filters with configurable input and output bit widths and automatic arithmetic saturation of the output to prevent numeric rollover distortion.

Key features

  • Efficient, multiplier-free design minimizes resource utilization and power consumption
  • Configurable input and output widths
  • Multiple tap-length configurations including 9-tap, 7-tap, and 5-tap
  • Arithmetic overflow output monitor
  • Clock enable
  • Output saturation prevents arithmetic rollover
  • Static resettable output
  • Registered input, registered output
  • Clock rates over 714 MHz supported
  • Includes complete simulation and verification software support suite
  • Custom designs and configurations available

Block Diagram

Benefits

  • Corrects frequency distortion due to DAC sin(x)/x response
  • Highly efficient multiplierless implementation
  • Highly configurable
  • Low complexity for hardware and power efficiency
  • Custom designs and configurations available

Applications

  • Signal Generators
  • Modulators
  • Test Equipment
  • Audio Systems

What’s Included?

  • Product License
  • EDIF or NGC core or source code
  • Verilog Test Bench
  • Supporting Matlab/Octave code for test vector generation
  • Verilog simulation model
  • Product Documentation

Specifications

Identity

Part Number
AH1002-DCF
Vendor
Anchor Hill Communications
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is DAC Correction Filter?

DAC Correction Filter is a DAC IP core from Anchor Hill Communications listed on Semi IP Hub.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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