What is CML I/O Pad Set?
CML I/O Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
Aragio Solutions
Category:
GPIO
CML I/O Pad Set
The CML library provides a differential clock driver, a voltage reference, and power cells to support REFCLK signaling for PCIe a…
Overview
The CML library provides a differential clock driver, a voltage reference, and power cells to support REFCLK signaling for PCIe applications.
What’s Included?
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 16nm | 16nm 160 nm | Silicon Proven |
Specifications
Identity
Part Number
RGO_TSMC16_18V18_FFC_45C_CML
Vendor
Aragio Solutions
Type
Silicon IP
Provider
HQ:
USA
Frequently asked questions about GPIO Pad Library IP cores
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.