CC-100IP-RF Analog and RF Sensitivity Enhancement IP

The CC-100IP-RF is a RF and Analog Frontend Sensitivity Enhancement IP Block that embeds a Hyper-Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and Energy Harvesting capabilities. The IP accomplishes Signal Sensitivity Enhancment by improving the PSRR of sensitive RF and Analog front end receivers. CC-100IP-RF Hyper-Bypass Capacitor creates an adjustable Impedance controlled point in IC power grids aiding in maximum on chip supply line filtering, Impedance matching for Power Grid flat frequency response, showing an up to a 600X improvement in effective and reservoir capacitance. The IP features a circuit noise activated dynamic input current controlled reservoir capacitance, and can function as a “stand-alone” on Chip DCAP, or work in parallel with existing DCAP structures. Due to the embedded IP negative feedback, the CC-100 features a 25% reduction in Hyper-Capacitor effective series inductance (ESL). The IP operates by feeding back a portion (nominally 20%) of the bypass current flowing through IP input base capacitors, feeding back current onto the chip power grid, preventing bypass Capacitor Deep discharge, thus reducing overall chip dynamic power draw. These effects substantially reduce RF Emissions and increase RF sensitivity for RF and Analog Frontends, making them more sensitive to input signaling, making systems less vulnerable to cyber hacking, and more secure The IP draws no current for operation, thus maximizing block efficiency.
The RF sensitivity Enhanced Hyper Cap IP is meant to replace or work in parallel with existing on chip decoupling capacitors, thus can be shaped into various aspect ratios and sizes to fit on-chip “white space”, the area under power grids, etc. in the same fashion as typical on-chip decoupling capacitors. In similar fashion to typical decoupling capacitors, the IP blocks can be connected in parallel to increase overall Power Grid Impedance Matching, RF emission reduction, reservoir capability, and effective capacitance.

• Enhances the Sensitivity of Analog and RF Frontend Receivers
• Enhances the PSRR od Analog and RF Frontend Receivers
• Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
• Up to a 36% Dynamic Power and RF Emissions Reduction
• On-Chip Cybersecurity Enhancement
• 25% Reduction in Capacitor ESL
• Provides the lowest impedance point in IC power-grids
• Can work in parallel with existing IC DCAPs
• Fits into any On chip footprint
• Ability to port to any manufacturing process
• Customizable design is not needed to support the operation of the device or IP.

• Enhances the Sensitivity of Analog and RF Frontend Receivers
• Enhances the PSRR od Analog and RF Frontend Receivers
• Enables Lowest Possible Dynamic Power Dissipation and RF Emissions
• Activates when the System/Chip is Active(Circuit noise activated)
• Enables Lowest possible Supply Line Noise--increasing IC sensitivity
• Creates the lowest Impedance point in IC Power-Grids
• Suppresses Frequencies Hackers use to gain access to Computers and embedded systems
• No software to load for block activation
• Adjustable Aspect ratio--fits into any circuit area,
• Draws No DC power for Operation

• Analog and RF Frontend Sensitivity Enhancement
• Analog and RF Frontend PSRR Enhancement
• Adjustable Power Grid Impedance Control
• On chip DCAP replacement--At least a 600X increase in effective capacitiance
• Power Supply Decoupling in ICs
• RF Emissions reduction
• Dynamic Power reduction
• Power Reduction and Cyber Security Enhancements in Digital, Mixed Signal, and Processor chips

• Working Silicon Loaner Samples
• Behavioral Model
• Datasheet
• .gds view
• LEF view
• 2 to 3 week custom spin time
• Customizable Circuit Design
• Design Support
• Datasheet-cut and paste the URL into a web browser to view.
• Behavioral Model-cut and paste the URL into a web browser to view.