Vendor: SmartDV Technologies Category: I2C / I3C

AVSBus Verification IP

AVSBus Verification IP provides a smart way to verify the AVSBus (Adaptive Voltage Scaling) component of a SOC or a ASIC.

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Verification IP View all specifications

Overview

AVSBus Verification IP provides a smart way to verify the AVSBus (Adaptive Voltage Scaling) component of a SOC or a ASIC. The SmartDV's AVSBus Verification IP is fully compliant with standard PMBus 1.3.1 Part III Specification and provides the following features.

AVSBus Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AVSBus Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Follows AVSBUS specification as defined in PMBus version 1.3.1 Part III Specification.
  • Supports data width up to 64 bits.
  • Support AVSBus Master and Slave Functionality.
  • Supports 3-wire, 2-wire AVSBus interface.
  • Supports all AVSBus Commands as per specs.
  • Supports Clock Resynchronization.
  • Support timeout detection and generation.
  • Supports Master Alert Generation.
  • Supports back to back commands.
  • Supports user response frame.
  • Supports Clock Suspension.
  • Supports following AVSBus topologies
  • o Single Master and Single Slave.
  • o Multiple links.
  • Supports Frame Alignment.
  • Supports insertion of various errors
    • Start code error
    • CRC error
    • Selector error
    • Command type error
    • Command group error
    • Command data type error
    • Unavailable Resource error
    • Invalid reserved bit error
    • Invalid values on SDATA and MDATA when clock suspension error
  • Built in functional coverage analysis.
  • Supports Callbacks in Master, Slave and Monitor for modifying and sampling data/command on AVSBus.
  • Notifies the test bench of significant events such as transactions, warnings and protocol violations. This can be written to separate log files.
  • AVSBus Verification IP comes with complete testsuite to test every feature of AVSBus specification.

Block Diagram

AVSBus VIP block diagram

Benefits

  • Faster testbench development and more complete verification of AVSBus designs.
  • Easy to use command interface simplifies testbench control and configuration of slave and master.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the AVSBus testcases.
  • Examples showing how to connect various components, and usage of Master, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
AVSBus VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about I2C / I3C IP cores

What is AVSBus Verification IP?

AVSBus Verification IP is a I2C / I3C IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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