Vendor: SmartDV Category: I2C / I3C

AVSBus Synthesizable Transactor

AVSBus Synthesizable Transactor provides a smart way to verify the AVSBus component of a SOC or a ASIC in Emulator or FPGA platfo…

Overview

AVSBus Synthesizable Transactor provides a smart way to verify the AVSBus component of a SOC or a ASIC in Emulator or FPGA platform.The SmartDV's AVSBus (Adaptive Voltage Scaling) Synthesizable Transactor is fully compliant with standard AVSBus Specification and provides the following features.

Key features

  • Follows AVSBus basic specification as defined in PMBus 1.3.1 Part III Specification
  • Supports data width upto 64 bits
  • Support AVSBus Master and Slave functionality
  • Supports 3-wire ,2-wire AVSBus interface
  • Supports all AVSBus Commands as per specs
  • Supports clock Resynchronization
  • Supports timeout detection and generation
  • Supports following AVSBus topologies
    • Single Master and Single Slave
    • Multiple links
  • Supports insertion of various errors
    • NACK insertion by Slave
    • CRC Error

Block Diagram

AVSBus Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Complete regression suite containing all the LVDS testcases
  • Synthesizable transactors
  • Examples showing how to connect and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Specifications

Identity

Part Number
AVSBus Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about I2C / I3C IP core

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As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about I2C / I3C IP cores

What is AVSBus Synthesizable Transactor?

AVSBus Synthesizable Transactor is a I2C / I3C IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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