AP Memory UHS PSRAM Controller

Most wearables devices typically monitor a finite set of parameters which does not demand a lot of computing power and memory size. Thus any wearable design requires low power, lower RAM density and simplified interface with optimal performances. These design requirements make PSRAM a natural choice for wearable applications. PSRAM has the advantages that there is no need of refresh control from external sources (unlike SDRAM) and active and standby currents are very low, therefore it has been adopted in many battery-operated mobile applications such as cellular phones and recently making its way into wearables and loT applications. The UHS product of PSRAM greatly reduces the power consumption compared to regular LPDRAM at high frequencies which helps to improve the battery life of wearable devices. Mobiveil’s approach on this emerging scenario results in a PSRAM controller named “UHS OPI PSRAM controller”. This controller supports AP Memory’s UHS series of high speed PSRAM devices which can clock frequencies of upto 1066 MHz. This controller enables smooth integration of APMemory’s UHS OPI PSRAM memory device chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.

• Device Supported:
  • Compatible with following UHS OPI PSRAM devices from APMemory - 8 bit data bus – DQ[7:0] support for AP325608AOKx device - 16 bit data bus – DQ[15:0] support for AP325616AOKx device
• Other Features:
  • Memory mapped access to the connected PSRAM Device
  • Octal SPI Interface with DDR mode access support
  • Wrap transfer support
  • Continuous mode Burst transfer support for efficient memory access
  • Auto-initiate feature to reduce F/W overhead
  • AXI4 system interface for memory access with outstanding address support.
  • APB port for control registers accesses
  • Features like Global Reset, Self Refresh and ZQ Calibration modes control through simple CSR access
  • Reference PHY model for easier technology specific integration and implementation

• Highly modular and programmable design
• Fully synchronous design
• Software control for key features

• Product Package
  • RTL Code
  • System Verilog/UVM based Testbench
  • Test cases
  • Protocol checkers and bus watchers
• Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide
• Licensing Options
  • Single Design or Multi-project license (HDL Source Code).