TSMC CLN22ULP 22nm DDR DLL - 160MHz-800MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
- TSMC
- 22nm
- ULP
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
TSMC CLN22ULP 22nm DDR DLL - 160MHz-800MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN22ULP 22nm DDR DLL - 253MHz-1265MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN12FFCLLLVT 12nm DDR DLL - 270MHz-1350MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN12FFCLLLVT 12nm DDR DLL - 360MHz-1800MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN12FFCLLLVT 12nm DDR DLL - 568MHz-2840MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN12FFCLL 12nm DDR DLL - 188MHz-940MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN12FFCLL 12nm DDR DLL - 250MHz-1250MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
TSMC CLN12FFCLL 12nm DDR DLL - 395MHz-1975MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L14LLP 14nm DDR DLL - 120MHz-600MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L14LLP 14nm DDR DLL - 160MHz-800MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L14LLP 14nm DDR DLL - 253MHz-1265MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LLP 12nm DDR DLL - 120MHz-600MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LLP 12nm DDR DLL - 160MHz-800MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
GF L12LLP 12nm DDR DLL - 253MHz-1265MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise f…
UMC L28HPCLVT 28nm Clock Generator PLL - 220MHz-1100MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HPCLVT 28nm Clock Generator PLL - 440MHz-2200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HPCLVT 28nm Clock Generator PLL - 880MHz-4400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HPC+LVT 28nm Clock Generator PLL - 225MHz-1125MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HPC+LVT 28nm Clock Generator PLL - 450MHz-2250MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L28HPC+LVT 28nm Clock Generator PLL - 900MHz-4500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.