UMC L65LP 65nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- UMC
- 65nm
- LP
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
UMC L65LP 65nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L55LP 55nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L55LP 55nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L55LP 55nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L40LP 40nm Clock Generator PLL - 75MHz-375MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L40LP 40nm Clock Generator PLL - 150MHz-750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L40LP 40nm Clock Generator PLL - 300MHz-1500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L40G 40nm Clock Generator PLL - 170MHz-850MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L40G 40nm Clock Generator PLL - 340MHz-1700MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
UMC L40G 40nm Clock Generator PLL - 680MHz-3400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPL 28nm Clock Generator PLL - 110MHz-550MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPL 28nm Clock Generator PLL - 220MHz-1100MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPL 28nm Clock Generator PLL - 440MHz-2200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPM 28nm Clock Generator PLL - 175MHz-875MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPM 28nm Clock Generator PLL - 350MHz-1750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPM 28nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN20SOC 20nm Clock Generator PLL - 175MHz-875MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN20SOC 20nm Clock Generator PLL - 350MHz-1750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
PWM to Class D Amplifier Power Stage, SMIC 0.13um
The AR35S13A is a efficient H-BTL audio output driver IP for Class-D amplifier application.