D/A Converter IP, 10 bits, 1MHz, UMC 0.18um G2 process
10-Bit 1MHz R-2R Digital-to-Analog converter, UMC 0.18um GII Logic process.
- 10 Bit
- UMC
- 180nm
- G
Explore data converter IP cores for mixed-signal SoC, ASIC, and FPGA designs. This category includes a broad range of ADC IP, DAC IP, and Audio Codec IP cores used to bridge the analog and digital domains in embedded, industrial, automotive, consumer, and communications applications.
Data converter intellectual property is essential when a chip needs to sense, digitize, generate, or reconstruct real-world signals. These semiconductor IP blocks are commonly used in sensor interfaces, audio systems, control loops, wireless transceivers, instrumentation, edge AI devices, and power-sensitive embedded platforms.
Browse this category to compare analog and mixed-signal IP by architecture, resolution, sampling rate, power consumption, interface support, process compatibility, and application fit. Whether you need precision conversion, high-speed signal acquisition, or integrated audio conversion, this directory helps you identify the right data converter IP core for your next design.
D/A Converter IP, 10 bits, 1MHz, UMC 0.18um G2 process
10-Bit 1MHz R-2R Digital-to-Analog converter, UMC 0.18um GII Logic process.
D/A Converter IP, 10 bits, 80Msps, UMC 0.13um SP/FSG process
10-Bit 80MSPS current output dual channel Digital-to-Analog converter, UMC 0.13um Logic high speed process.
D/A Converter IP, 18 bits, 48KHz, UMC 0.11um HS/FSG process
18-Bit 48KHz Sampled Stereo Audio Digital-to-Analog converter with Headphone Driver, UMC 0.11um HS/FSG Logic process.
D/A Converter IP, 8 bits, 250Msps, UMC 0.11um HS/AE process
8-Bit 250MSPS 3-channle Current-steering Video Digital-to-Analog converter, UMC 0.11um HS/AE (AL Advance Enhancement) Logic proce…
Audio ADDA IP, 24 bits, 96KHz, UMC 90nm SP process
24-Bit 96KHz Audio Codec, UMC 90nm SP/RVT Logic 2.5OD3.3 Low-K process.
Audio ADDA IP, 18 bits, Audio Codec, UMC 90nm SP process
18-Bit MONO Sigma-Delta Audio Codec with speaker driver, UMC 90nm SP/RVT Low-K Logic process.
Audio ADDA IP, 24 bits, 96KHz, UMC 90nm SP process
24-Bit 96KHz Audio Codec, UMC 90nm SP/RVT 2.5OD3.3V Low-K Logic process.
Audio ADDA IP, 24 bits, 96KHz, UMC 90nm SP process
24-Bit 96KHz A/D onverter, 24-Bit 96KHz Digital-to-Analog converter, Audio Codec, UMC 90nm SP/RVT+HVT 2.5OD3.3 Logic process.
Audio ADDA IP, 24 bits, 96KHz, UMC 90nm SP process
24-Bit 96KHz A/D onverter, 24-Bit 96KHz Digital-to-Analog converter, Audio Codec, UMC 90nm SP/RVT Logic 2.5OD3.3 process.
Audio ADDA IP, 16 bits, Audio Codec, UMC 0.13um HS/FSG process
16-Bit Sigma-Delta Audio Codec, UMC 0.13um HS/FSG Logic process.
Audio ADDA IP, 16 bits, Audio Codec, UMC 0.13um HS/FSG process
16-Bit Sigma-Delta Audio Codec, UMC 0.13um HS/FSG Logic process.
Audio ADDA IP, 24 bits, 96KHz, UMC 0.13um LL/FSG process
24-Bit 96KHz Sampled Mono Audio CODEC with Class-D Speaker Driver, UMC 0.13um LL/FSG Logic process.
Audio ADDA IP, 24 bits, 96KHz, UMC 0.13um LL/FSG process
24-Bit 96KHz Sampled Mono Audio CODEC with Speaker Driver, UMC 0.13um LL/FSG Logic process.
Audio ADDA IP, 16 bits, Audio Codec, UMC 0.13um HS/FSG process
16-Bit Sigma-Delta Audio Codec, UMC 0.13um HS/FSG Logic process.
Audio ADDA IP, 24 bits, 96KHz, UMC 0.11um HS/FSG process
24-Bit 96KHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver, UMC 0.11um HS Logic process.
Audio ADDA IP, 24 bits / 96KHz, UMC 0.11um HS/AE process
24-Bit 96KHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Audio ADDA IP, 24 bits / 96KHz, UMC 0.11um HS/AE process
24-Bit 96KHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver, UMC 0.11um HS/AE Logic process.
A/D Converter IP, 11 bits, 1Msps, UMC 90nm LL process
It is a 11-Bit 1MSPS SAR Analog-to-Digital converter, UMC 90nm LL/RVT Low-K process.
A/D Converter IP, 10 bits, 1Msps (Max clock rate: 13MHz), with 8-to-1 input MUX, UMC 90nm SP process
FXAnalog-to-Digital converter143HD0A with 8-to1 Mux for FTC, UMC 90um SP/RVT Low-K Logic process.
A/D Converter IP, 11 bits, 1Msps (Max clock rate: 13MHz), with 8-to-1 input MUX, UMC 90nm SP process
SAR Analog-to-Digital converter with 8-to-1 Mux and resistor-type touch panel deriver, UMC 90nm SP/RVT Low-K process.