ADC IP cores (Analog-to-Digital Converter IP) convert analog signals into digital data in modern SoC and ASIC designs, enabling interaction with real-world signals such as sensors, audio, and RF inputs.
These IP cores support various architectures including SAR ADC, pipeline ADC, and sigma-delta ADC, each optimized for different trade-offs between speed, resolution, and power consumption.
This catalog allows you to compare ADC IP cores from leading vendors based on resolution (bits), sampling rate, power efficiency, and process node compatibility.
Whether you are designing sensor interfaces, audio systems, industrial control applications, or RF front-ends, you can find the right ADC IP for your design.
14-bit, 300 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B300M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni D…
5 MHz 14-bit 2 channel 300 kSPS cascade delta-sigma ADC
The block is fourth order cascade (2-2) delta-sigma ADC with 5-level quantizers in both stages.
12-bit 1-channel 44/70/90 MSPS pipeline ADC
180TSMC_ADC_13 is a low-power high-speed 12 bit ADC that employs high-performance differential pipeline architecture.
2-bit 2-channel 50 MSPS flash ADC
The circuit is 2-bit ADC with programmable threshold.
2-bit 2-channel 100 MSPS flash ADC
The circuit is 2-bit ADC with programmable threshold.
12-bit 1-channel 20 to 100 MSPS ADC
The low-power high-speed 12-bit ADC employs a high-performance differential pipeline architecture.
12-bit 1-channel 4 MSPS SAR ADC
065TSMC_ADC_10 employs high-performance differential successive approximation architecture with sub-ranging and output offset com…
12-bit 4-channel 20 to 100 MSPS ADC
Quad-channel 12-bit 20 – 100 MSPS ADC contains four ADC channels, LVDS receiver, reference voltages and reference currents circui…
The 10-bit 100 MSPS ADC employs a high-performance front-end sample-and-hold with differential multi-stage pipelined architecture…
12-bit 800 kSPS cascade delta-sigma ADC
The block is third order cascade (2-1) delta-sigma ADC with 5-level quantizers in both stages.
14-bit 1-channel 100/125 MSPS pipeline ADC
The high-speed 14-bit ADC employs a high-performance differential pipeline architecture.
Ultra Low Power 8-bit ADC - Ultra Low Voltage (1V), Ultra Low Power (850nA) - LFoundry 0.15µm
This macro-cell is a general purpose, ultra low power, 8-bit, time-based Analog-to-Digital Converter (ADC) core designed for LFou…
14-bit 1-channel 50 MSPS pipeline ADC
The ADC has built on pipelined architecture.
14-bit 12.5MSPS SAR ADC - Tower 65nm
The A14B12p5M is a high-performance, low-power analog-to-digital converter (ADC) intellectual property (IP) block designed for ap…
Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
The ODT-ADS-7B64G-3 is an ultra-high-bandwidth time-interleaved ADC designed in a 3nm CMOS process.
The ODT-ADS-12B9G-16 is an ultra-highperformance time-interleaved ADC designed in a 16nm CMOS process.
7 Bit 6 GS/s Folding ADC on Fujitsu 55 nm CS250L
The IP consists of a 7 bit monolithic folding ADC clocked externally for 6 GS/s.
Auxiliary DAC - 12-bit Successive Approximation Register (SAR) DAC
This digital-to-analog converter implements segmented R-2R and thermometer decoder architecture to achieve 12-bit resolution.
12-bit, 8 GSPS High Performance ADC in 16nm CMOS
The ODT-ADS-12B8G-16 is an ultra highperformance time-interleaved ADC designed in a 16nm CMOS process.
HCLTech offers SAR ADC 10bit hcl_saradc_10bit_5msps_t40_v1 is a general-purpose analog to digital converter (ADC).