Vendor: MIPS Category: Edge AI Accelerator

AI inference engine for real-time edge intelligence

Today’s robots specialize in narrowly defined tasks, built for simple automation of repetitive behavior.

Overview

Today’s robots specialize in narrowly defined tasks, built for simple automation of repetitive behavior. The next generation of autonomous platforms will be more advanced and adaptable to new tasks, environments, and events as part of the physical AI market. These platforms will think and make decisions for a variety of use cases:

Automotive

  •  Autonomous Vehicles (L2+ AV)
  •  Advanced Driver Assistance Systems (ADAS)
  •  Natural Language Processing for In Vehicle Information Systems (IVI)

Industrial

  •  Predictive Maintenance
  •  Quality Control
  •  Energy Management
  •  Natural Language Processing for Safety and Control systems
  •  Smart Manufacturing
  • Surgical Assistance
  •  Medical Imaging
  •  Pest Detection
  •  Precision Farming
  •  Crop Monitoring

Self-directed robots, capable of evaluating and planning autonomously, will fit more easily into the human world to drive scale, consistency, and safety in many industries. From enabling better control interfaces to quickly adapting to new processes, physical AI at the edge makes machines better.

Real-time intelligence is the essential tech stack for physical AI. The MIPSTM S8200 enables the capabilities of multi-modal AI to deliver mixture-of-experts processing at the edge. Build physical AI applications with open-source, commercial, or self-developed models to dial-in the inference capabilities of the physical AI platform.

Aiming to enable a 4X higher TOPS/W (tera operations per second, per Watt) output, the MIPS S8200 is built out of quad-core building blocks, featuring multiple-thread support, and tiling of coherent clusters for scaling up into large designs. The MIPS S8200 AI inference engine maybe integrated into SoC designs, chips based on MIPS reference silicon, or custom-tailored solutions.

The MIPS S8200 will feature highly-efficient RISC-V application cores with tightly-coupled AI engines. Capable of running vector or matrix workloads, these engines provide support for deep learning frameworks (PyTorch, Tensorflow, and others) with MIPS optimized compilers and libraries.

With industry-leading performance combined with a power-efficient, open-specification based design, adopting physical AI in autonomous platforms will be easier than ever before.

Key features

  • Flexible Models: Bring your physical AI application, open-source, or commercial model
  • Easy Adoption: Based on open-specification RISC-V ISA for driving innovation and leveraging the broad community of open-source and commercial tools
  • Scalable Design: Turnkey enablement for AI inference compute from 10’s to 1000’s of TOPS

Applications

  • Automotive
    •   Autonomous Vehicles (L2+ AV)
    •   Advanced Driver Assistance Systems  (ADAS) 
    •  Natural Language Processing for In Vehicle Information Systems (IVI)
  •  Industrial
    •   Predictive Maintenance
    •   Quality Control 
    •  Energy Management
    •   Natural Language Processing for Safety and Control systems
    •   Smart Manufacturing
    •   Surgical Assistance
    •   Medical Imaging
    •   Pest Detection
    •   Precision Farming
    •   Crop Monitoring

Specifications

Identity

Part Number
S8200
Vendor
MIPS
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Edge AI Accelerator IP core

Introducing MIPS Sense data movement engines

Autonomous platforms sense the world around them with a variety of inputs, from radar, lidar, and cameras, to gyroscopes, accelerometers, and atmospheric sensors. These sensors are rapidly increasing in fidelity with more resolution, color depth, accuracy, and increased sampling periods generating exponentially more data.

RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI

While lightweight architectures like MobileNetV2 employ Depthwise Separable Convolutions (DSC) to reduce computational complexity, their multi-stage design introduces a critical performance bottleneck inherent to layer-by-layer execution: the high energy and latency cost of transferring intermediate feature maps to either large on-chip buffers or off-chip DRAM. To address this memory wall, this paper introduces a novel hardware accelerator architecture that utilizes a fused pixel-wise dataflow.

Accelerating Your Development: Simplify SoC I/O with a Single Multi-Protocol SerDes IP

Enter the Multi-Protocol SerDes (Serializer/Deserializer)—a flexible, reusable IP block that allows a single PHY to support multiple serial communication protocols, such as PCIe, SATA, Ethernet, USB, and more. This approach enables SoC vendors to meet diverse customer requirements and application needs without redesigning I/O for each target market.

Frequently asked questions about Edge AI Accelerator IP cores

What is AI inference engine for real-time edge intelligence?

AI inference engine for real-time edge intelligence is a Edge AI Accelerator IP core from MIPS listed on Semi IP Hub.

How should engineers evaluate this Edge AI Accelerator?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Edge AI Accelerator IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP