AES IP Core
AES IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Encryption Standard (AES) specification in "F…
Overview
AES IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197". This standard specifies the Rijndael algorithm, a symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, and 256 bits.
Countermeasures against side-channel attacks are implemented in the AES IP Core. Procenne AES IP Core is compatible with Xilinx FPGAs and INTEL FPGAs. VHDL is used as the Hardware Description Language of the IP Core. ECB, CBC, CTR, and GCM mode of operations are supported and implemented according to "NIST SP800-38a" and "NIST SP800-38d".
Key features
- supports encryption and decryption for modes listed below:
- ECB, CBC, CTR mode of operations
- optional support for GCM
- supports 128, 192, and 256-bit key lengths
- has masked and non-masked modes
- is compliant with FIPS 197
- has fully scalable input and output interfaces
Block Diagram
What’s Included?
- IP can be licensed as;
- Single project license
- Multi-project license
- Delivery type of the IP can be;
- Encrypted Netlist
- Encrypted RTL
- SUPPORT
- First-year M&S is mandatory. Customers receive IP updates and phone and email support related to the IP core under the M&S agreement
Specifications
Identity
Security
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Symmetric Cryptography IP cores
What is AES IP Core?
AES IP Core is a Symmetric Crypto IP core from ElectraIC listed on Semi IP Hub.
How should engineers evaluate this Symmetric Crypto?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.