8-bit FAST Microcontrollers Family

The DF6805 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. The DF6805 soft core is binary-compatible with the industry standard Motorola 68HC05 8-bit microcontroller. It can achieve a performance of 45 - 100 million instructions per second. The DF6805 has a FAST architecture that is 4.1 times faster, compared to original implementation. In the standard configuration, the core has integrated on chip, major peripheral functions.
The DF6805 Microcontroller Core contains full-duplex UART- Asynchronous Serial Communication Interface (SCI) and can also be equipped with the Synchronous Serial Peripheral Interface (SPI).
The main 16-bit, free-running timer system has two input capture lines and two output-compare lines.
Self-monitoring circuitry is included on-chip, to protect against system errors. The Computer Operating Properly (COP) watchdog system, protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt, if illegal opcode is detected.
Two software-controlled power-saving modes - WAIT and STOP, are available to conserve additional power. These modes make the DF6805 IP Core especially attractive for automotive and battery-driven applications.
The DF6805 is fully customizable, - it is delivered in the exact configuration to meet user's requirements. There is no need to pay extra, for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.

Each of the DCD's DF68XX Core has built-in support for the DCD Hardware Debug System, called DoCD . It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).

Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.

• FAST architecture - 4.1 times faster than the original implementation
• Software compatible with 68HC05 industry standard
• 11 times faster multiplication
• 64 bytes of System Function Registers space (SFRs)
• Up to 64K bytes of Data Memory
• Up to 64K bytes of Code Memory
• De-multiplexed Address/Data Bus to allow easy memory connection
• Two power saving modes: STOP, WAI
• Ready pin allows Core to operate with slow program and data memories.
• Fully synthesizable
• Static synchronous design
• No internal reset generator or gated clock
• Positive edge clocking and no internal tri-states
• Scan test ready
• 1 GHz of virtual clock frequency compared to original implementation

• HDL Source Code
• Testbench environment
  • Automatic Simulation macros
  • Tests with reference responses
• Synthesis scripts
• Technical documentation
• 12 months of technical support