6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 uLL, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as sp…
Overview
Key features
- Ultra High Density
- Up to 15% smaller area after P&R compared to standard 7-Track library
- Pulsed latches as Spinner Cells instead of SCAN D-flip-flops: for 30% gain in density at cell level
- Metal layer 2 available for routing as only Metal 1 used for cell design
- 6-Track cells for optimal area reduction
- Configuration
- uLL MOS versions for the lowest dynamic power and leakage power
- Power reduction features
- 30% less consumption of dynamic power with 6 rather than usual 7 Tracks at 1.2 V+/-10%
- Low Voltage Capability for additional power savings when operating down to 1.0 V +/-10%
- Easy implementation
- Pulse generation automated by the script for Insert pulse generation
- Spinner cell design minimizing hold time violations
- Optimal Design for Yield
- Design methodology ensuring High-Yield circuits despite Mismatch
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 90nm | CIS | Pre-Silicon |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about standard cell libraries
What is 6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability?
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability is a Standard Cell Libraries IP core from Dolphin Semiconductor listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.
How should engineers evaluate this Standard Cell Libraries?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Standard Cell Libraries IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.