Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
SMIC
Category:
SRAM
55LL general SP SRAM compiler with HVT bit cell.
55LL general SP SRAM compiler with HVT bit cell.
Overview
55LL general SP SRAM compiler with HVT bit cell.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 55nm | LL | In Production |
Specifications
Identity
Part Number
S55NLLGSPH
Vendor
SMIC
Type
Silicon IP
Provider
HQ:
China
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Frequently asked questions about SRAM IP cores
What is 55LL general SP SRAM compiler with HVT bit cell.?
55LL general SP SRAM compiler with HVT bit cell. is a SRAM IP core from SMIC listed on Semi IP Hub. It is listed with support for smic In Production.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.