Learn more about Analog IP core
The authors present MEGATRON, a heterogeneous Edge GenAI System-on-Chip in 28nm FD-SOI CMOS technology combining a non-volatile analog in-memory-computing engine based on a 4Mi-cell phase-change memory (PCM) array with a digital RISC-V-based flexible neural processing unit.
With modern chips, power management sits right at the core of the architecture. Between scaling down to advanced nodes and pushing for maximum performance-per-watt, managing power has become one of the most complex, high-risk parts of silicon design. Here is what engineering teams are actually dealing with.
Mixed-signal SoCs rely on nominally input-only analog pins to acquire off-chip signals, but the directionality of these interfaces is generally treated as a functional property rather than explicitly verified as a security property. This work identifies and experimentally demonstrates a directionality-based class of analog and mixed-signal (AMS) exfiltration attacks in which data-dependent circuit-offset modulation converts a nominally input-only pin into an outbound information channel.
This Agile Analog blog post outlines the security certification process and the impact of implementing analog anti-tamper solutions. With new security measures such as the EU’s Cyber Resilience Act (CRA) regulations becoming fully enforced in 2027, there is increasing interest in security certification and the analog IP that companies can use to detect and prevent security attacks.
Low-power event-based Analog Front-Ends (AFEs) are essential for building efficient, end-to-end neuromorphic signal processing systems. In this paper, the authors present an event-based AFE Application-Specific Integrated Circuit (ASIC) optimized for biomedical signal acquisition and encoding.
The costs of designing and producing an analog ASIC can be grouped into three parts: human capital, software tools, and prototype fabrication
