Vendor: Synopsys, Inc. Category: Multi-Protocol PHY

12G PHY, UMC 28HPC x2, North/South (vertical) poly orientation

The multi-lane Multi-Protocol 16G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…

Overview

The multi-lane Multi-Protocol 16G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 16G PHY delivers exceptional signal integrity and jitter performance that exceeds the standards electrical specifications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards including PCI Express, SATA, Ethernet, OBSI/CPRI, JESD204, Serial Rapid I/O and other industry-standard interconnect protocols. The Synopsys Multi-Protocol 16G PHY IP is optimized to meet the needs of applications with high-speed port side, chip-to-chip, and backplane interfaces.

The configurable transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY supports low standby power with advanced L1 substates and low active power with I/O supply under drive, decision feedback equalization (DFE) bypass and V-Boost off. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerate time-to-market.

Key features

  • Supports 1.25 to 16 Gbps data rates
  • Supports
    • PCI Express 4.0/3.1/2.1/1.1, with lane margining
    • IEEE 802.3 1G to 40G backplane (KX, KX4/XAUI, KR & KR4), port side (XFI, SFF-8431/SFI and CR4)
    • SGMII and QSGMII (1.25 to 5G)
    • SATA 6G/3G/1.5G
    • CEI-6G and CEI-11G
    • Serial Rapid IO (SRIO)
    • CPRI, OBSAI, JESD204B
    • Other industry-standards
  • Supports x1 to x16 macro configurations
  • Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
  • PCI Express L1 substate power management
  • PCI Express aggregation and bifurcation
  • Spread Spectrum Clock (SSC)
  • PCIe Separate Refclk Independent SSC (SRIS)
  • Reference clock sharing for aggregated macro configurations
  • Embedded bit error rate (BER) tester and internal eye monitor
  • IEEE 802.3az Electrical Energy Efficient (EEE)
  • Supports IEEE 1149.6 AC Boundary Scan
  • Supports -40°C to 125°C Tj

Block Diagram

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC

Specifications

Identity

Part Number
dwc_12g_phy_umc28hpc_x2ns
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

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Provider

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 12G PHY, UMC 28HPC x2, North/South (vertical) poly orientation?

12G PHY, UMC 28HPC x2, North/South (vertical) poly orientation is a Multi-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for umc.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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