12-bit 500 MSPS IQ DAC

The 12-bit 500 MSPS IQ DAC employs a high-performance current steering architecture and provides optional differential current output or differential voltage output. The bandgap and current source included to provide a complete DAC. The DAC can be configured to adjust full-scale output range. The DAC uses segmentation architecture combined with Q2 Random Walk algorithm to achieve excellent dynamic and static performance, wide output bandwidth. An internal resistive load together with current source is used to set differential voltage output, which independent from process, supply and temperature.
The block is designed on TSMC CMOS 65 nm technology.

• TSMC CMOS 65 nm
• Resolution 12 bit
• Current-sinking DAC
• Different power supplies for digital (1.2 V) and analog parts (2.5 V)
• Sampling rate up to 500 MSPS
• Optional internal differential resistive load
• Adjustable full-scale output range
• Dynamic performance:
  • 81.3 dB SFDR, 73.1 dB SNR at 500 MSPS and fin=10 MHz
  • 77.5 dB SFDR, 72.7 dB SNR at 500 MSPS and fin=20 MHz
  • 63.4 dB SFDR, 74.0 dB SNR at 500 MSPS and fin=70 MHz
  • 56.3 dB SFDR, 71.7 dB SNR at 500 MSPS and fin=150 MHz
• Differential non-linearity 0.18 LSB
• Integral non-linearity 0.5 LSB
• Compact die area 0.47 mm2
• Portable to other technologies (upon request)

• Wireless infrastructures
• Broadband communications
• Picocell, femtocell base stations
• Medical instrumentation
• Ultrasound transducer excitation
• Signals and arbitrary waveform generators

• Schematic or NetList
• Abstract view (.lef and .lib files)
• Layout (optional)
• Verilog behavior model
• Extracted view (optional)
• GDSII
• DRC, LVS, antenna report
• Test bench with saved configurations (optional)
• Documentation