DAC 2024 - Showcasing the future of RISC-V through EDA
Brett Cline, Codasip
Vendor:
NTLab
Category:
DAC
12-bit 2-channel up to 50 MSPS current steering DAC
180TSMC_DAC_07 is a 12-bit 50 MSPS dual current steering DAC contains two DAC cores, reference current, bandgap, configuration re…
Overview
180TSMC_DAC_07 is a 12-bit 50 MSPS dual current steering DAC contains two DAC cores, reference current, bandgap, configuration register. Core DAC is based on current steering architecture and contains control logic, current source, switches array and reference voltage. There are two operation modes: with external reference current and internal reference current, which independent from voltage supply, temperature and dependent from process variations of resistor. DAC has a feature of adjusting output current. A segmented DAC architecture and Q2 random walk algorithm are used. DAC requires: 3.0 ÷ 3.6 V analog supply, 3.0 ÷ 3.6 V digital supply, differential input clock signal with duty cycle 45 ÷ 55%. 12-bit 50 MSPS dual current steering DAC supports standby mode.
Key features
- TSMC CMOS 180 nm
- Resolution 12 bit
- Dual channel
- Different power supplies for digital (3.3 V) and analog parts (3.3 V)
- Sampling rate up 50 MSPS
- Standby mode (current consumption <100 nA)
- Power dissipation:
- 75.24 mW at 50 MSPS and 10 mA output current
- Differential current output range from 5 mA to 20 mA
- Spurious-free dynamic range:
- 87 dB at 50 MSPS and fin = 1.575 MHz and 10 mA output current
- 88 dB at 50 MSPS and fin = 11.513 MHz and 10 mA output current
- Signal-to-noise ratio:
- 70 dB at 50 MSPS and fin = 1.575 MHz and 10 mA output current
- 70 dB at 50 MSPS and fin = 11.513 MHz and 10 mA output current
- Signal-to-noise and distortion ratio:
- 70 dB at 50 MSPS and fin = 1.575 MHz and 10 mA output current
- 70 dB at 50 MSPS and fin =11.513 MHz and 10 mA output current
- Die area 0.67 mm2
- Portable to other technologies (upon request)
Block Diagram
180TSMC_DAC_07 block diagram
Applications
- Wireless infrastructures
- Broadband communications
- Picocell, femtocell base stations
- Medical instrumentation
- Ultrasound transducer excitation
- Signals and arbitrary waveform generators
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | BCDG2 | Silicon Proven |
Specifications
Identity
Part Number
180TSMC_DAC_07
Vendor
NTLab
Type
Silicon IP
Analog
Resolution bits
12 Bit
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Lithuania
Learn more about DAC IP core
Making the most of the 60th DAC
Brett Cline, Codasip
DAC 2022 - Is it too risky not to adopt RISC-V?
Brett Cline, Codasip
Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
DAC: The View from Wall Street
DAC Panelists Discuss Emulation's Versatility & Various Use Models
Lauro Rizzatti, Verification Consultant
Frequently asked questions about DAC IP cores
What is 12-bit 2-channel up to 50 MSPS current steering DAC?
12-bit 2-channel up to 50 MSPS current steering DAC is a DAC IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this DAC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.