Vendor: NTLab Category: DAC

12-bit 16-channel 1 MSPS R/2R DAC

The 16 channels 12-bit R/2R DAC contains a three principal blocks: adjustable bias, DAC core and logic block.

12 Bit TSMC 90nm CIS View all specifications

Overview

The 16 channels 12-bit R/2R DAC contains a three principal blocks: adjustable bias, DAC core and logic block. DAC core consist of 16 identical R/2R DAC, each of which include differential R/2R ladder and output operational amplifier AB class. There is a possibility to turn off each output channels and whole scheme Digital control register adj<15:4> sets optimal mode by reducing current consumption. It corrects output buffers current, common mode and swing output signal. DAC requires 1.62 ÷ 1.98 V (port Vdd18) analog supply and 0.9 ÷ 1.1 V (port Vdd) digital supply.

Key features

  • TSMC 90 nm MS CMOS
  • R/2R architecture
  • Resolution 12 bit
  • 1 MHz sampling rate
  • Different power supplies for digital (1.0 V) and analog (1.8 V) parts
  • Standby mode (current consumption <650 nA)
  • 11.9 mW power dissipation
  • 0.74 LSB maximum differential nonlinearity
  • 1.20 LSB maximal integrated nonlinearity
  • 278 ns time setup
  • Small area
  • Portable to other technologies (upon request)

Block Diagram

Applications

  • Industrial process control
  • Automated test equipment
  • Digital calibration
  • Data acquisition systems
  • Motion control systems

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 90nm CIS

Specifications

Identity

Part Number
090TSMC_DAC_06
Vendor
NTLab
Type
Silicon IP

Analog

Resolution bits
12 Bit

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Lithuania

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 12-bit 16-channel 1 MSPS R/2R DAC?

12-bit 16-channel 1 MSPS R/2R DAC is a DAC IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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