11-bit, 2MSPS SAR ADC/DAC - 11-bit, 15MSPS, Hybrid SAR - AMS 0.35 um
This macro-cell is a general purpose, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) and Digital-to-An…
Overview
This macro-cell is a general purpose, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) subsystem. The DAC employs a hybrid architecture, using 6-bit resistive and 5-bit capacitive sub-DACs.
It is a standard part, enabling multiple system utilizations. The core operates in 11-bit linear mode and uses one 3.3V analog and one 3.3V digital supplies.
The core includes built-in sample-and-hold functionality.
Key features
- 11-bit/3.7 MSPS SAR ADC
- 11-bit/10.4 MSPS DAC
- Independent high and low reference inputs
- Digital parallel input,digital serial output
- End of conversion indicator
- Hold In and Hold Out auxiliary signals
- Indicative area:0.165mm2
Block Diagram
Specifications
Identity
Analog
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about ADC IP cores
What is 11-bit, 2MSPS SAR ADC/DAC - 11-bit, 15MSPS, Hybrid SAR - AMS 0.35 um?
11-bit, 2MSPS SAR ADC/DAC - 11-bit, 15MSPS, Hybrid SAR - AMS 0.35 um is a ADC IP core from Chipus Microelectronics listed on Semi IP Hub.
How should engineers evaluate this ADC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.