Vendor: Synopsys, Inc. Category: Multi-Protocol PHY

10G PHY for Differential Buffer, GF 12LP, North/South (vertical) poly orientation

The multi-channel PHY IP for PCI Express 3.1 includes the vendor’s high-speed, high-performance transceiver to meet today’s appli…

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GlobalFoundries 12nm LP View all specifications

Overview

The multi-channel PHY IP for PCI Express 3.1 includes the vendor’s high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Using the leading-edge design, analysis, simulation, and measurement techniques, the vendor delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.

The vendor offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, the vendor's solution is in volume production and has been successfully implemented in a wide range of applications.

Key features

  • Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
  • x1, x2, x4, x8, x16 lane configurations with bifurcation
  • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
  • L1 substate and SRIS support
  • Power gating and power island
  • Embedded Bit Error Rate (BER) tester and internal eye monitor
  • Build-in Self Test vectors, PRBS generation and checker
  • IEEE 1149. 6 AC JTAG Boundry Scan
  • Supports -40C to 125C junctions
  • Supports optional wirebond and flip-chip packaging

Block Diagram

dwc_diffbuf_gf12lp_ns block diagram

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP —

Specifications

Identity

Part Number
dwc_diffbuf_gf12lp_ns
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

Learn more about Multi-Protocol PHY IP core

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Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 10G PHY for Differential Buffer, GF 12LP, North/South (vertical) poly orientation?

10G PHY for Differential Buffer, GF 12LP, North/South (vertical) poly orientation is a Multi-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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