IPrium releases CCSDS TM Telemetry AR4JA LDPC Encoder and Decoder
FOGGIA, Italy, November 24, 2022 - FPGA intellectual property (IP) provider IPrium LLC has today announced that it has expanded its family of LDPC Encoder and Decoder IP products with a new AR4JA LDPC for CCSDS 131.0 Telemetry TM synchronization and channel coding standard.
The LDPC IP Core supports code rates 1/2, 2/3 and 4/5, information block sizes of 1024, 4906 and 16384 bits with low processing delay and significant coding gain. Main application of the AR4JA CCSDS LDPC is real-time telemetry in satellite communication systems.
Pricing and Availability
The CCSDS AR4JA LDPC Encoder and Decoder IP Core is available immediately in synthesizable Verilog or optimized netlist format, along with synthesis scripts, simulation test bench with expected results, and user manual. For further information, a product evaluation or pricing, please visit the IP Core page:
About IPrium LLC
IPrium Modem IP Cores allow designers of communication equipment to rapidly develop and verify their systems in a highly cost-effective manner. IPrium offers FPGA IP Cores for high-quality wireless and wireline modems. Visit IPrium at www.iprium.com.
Related Semiconductor IP
- CCSDS AR4JA LDPC Decoder & Encoder
- CCSDS AR4JA LDPC Encoder & Decoder
- CCSDS AR4JA LDPC Encoder and Decoder with code rates 1/2, 2/3, 4/5 and block sizes 1K, 4K, 16K
Related News
- IPrium releases CCSDS TC Telecommand LDPC Encoder and Decoder
- CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core Available For Licensing and Implementation from Global IP Core
- IPrium releases LunaNet AFS LDPC Encoder and Decoder for Lunar Navigation Satellite Systems
- Creonic to Supply New LDPC Decoder and Encoder IP Cores for CCSDS Standard
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA