Vendor: NTLab Category: DAC

10-bit 1-channel 100 MHz current DAC

The 10-bit dual high-speed DAC is based on current steering architecture, which provides high-speed conversion rate and good dyna…

10 Bit SMIC 180nm G Silicon Proven View all specifications

Overview

The 10-bit dual high-speed DAC is based on current steering architecture, which provides high-speed conversion rate and good dynamic performance. DAC consists of three principal blocks: adjustable reference voltage and current generator, decoding logic, current source and output switches array. Device has a feature of adjusting output current and entering sleep mode, turning the device off. DAC requires 1.8 V analog and digital supply, and digital and analog ground to work properly. Pins dac[2:0] adjust DAC output current.
The device is implemented on technology SMIC EEPROM CMOS 0.18 um.

Key features

  • SMIC EEPROM CMOS 0.18 um technology
  • Resolution 10 bits
  • 100 MSPS update rate
  • High spurious free dynamic range performance up to 25 MHz output
  • Adjustable output current (from 1.8 mA to 2 mA)
  • Sleep mode (current consumption less than 200 nA)
  • Portable to other technologies (upon request)

Block Diagram

Applications

  • Wireless infrastructures
  • Picocell, femtocell base stations
  • Medical instrumentation
  • Ultrasound transducer excitation
  • Signals generators, arbitrary waveform generators

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Silicon Options

Foundry Node Process Maturity
SMIC 180nm G Silicon Proven

Specifications

Identity

Part Number
180SMIC_DAC_01
Vendor
NTLab
Type
Silicon IP

Analog

Resolution bits
10 Bit

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Lithuania

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 10-bit 1-channel 100 MHz current DAC?

10-bit 1-channel 100 MHz current DAC is a DAC IP core from NTLab listed on Semi IP Hub. It is listed with support for smic Silicon Proven.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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