0.075 - 3 GHz quadrature former
This device is designed to generate a quadrature local oscillator signal.
Overview
This device is designed to generate a quadrature local oscillator signal. A quadrature generator circuit constructed in CMOS logic and consists of two converters ECL/CMOS, quadrature former with input frequency divider by 2 or 4, prescaler by 2, 4, 8, 16 and phase control block, with ability of fine tuning of output signal phase. To reduce phase noise output triggers are strobbed by high-frequency signal.
Key features
- TSMC CMOS 65 nm
- Output frequency range 0.075-3 GHz
- Input frequency division (by 2, 4, 8, 16, 32 or 64)
- High accuracy of the phase control
- Output signal strobbing
Block Diagram
Applications
- Quadrature signal processing for mixer
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 65nm | GP | Silicon Proven |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about RF Front End IP cores
What is 0.075 - 3 GHz quadrature former?
0.075 - 3 GHz quadrature former is a RF Front End IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this RF Front End?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this RF Front End IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.